1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of bipolar and CMOS transistors.
2. Background Art
In one type of bipolar transistor, and more particularly a heterojunction bipolar transistor (“HBT”), used as an example in the present application, a thin silicon-germanium (“SiGe”) layer is grown as the base of the bipolar transistor on a silicon wafer. The SiGe HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is considerably reduced. Cutoff frequencies in excess of 100 GHz have been achieved for the SiGe HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required.
In addition to the above stated speed and frequency response advantages of bipolar transistors, such as the SiGe HBTs, circuits used in modern electronic devices, such as cellular phones, laptop computers, and mobile communication networks, also require low power consumption and high noise immunity typically provided by CMOS transistors. In an attempt to combine the benefits of bipolar transistors, such as SiGe HBTs, with the bipolar transistors and CMOS transistors on the same die. For example, a circuit comprising a SiGe HBT and a CMOS transistor can be fabricated on the same substrate using Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) technology.
However, fabricating bipolar transistors and CMOS transistors on the same substrate can undesirably increase overall process complexity and manufacturing cost. Thus, semiconductor manufacturers are challenged to simplify process flow and reduce the manufacturing cost required to fabricate bipolar transistors and CMOS transistors on the same substrate.
In one approach, a gate for a CMOS transistor, such as a PFET, is formed in a CMOS region of a substrate and a collector is formed in a bipolar region of the substrate. A layer of dielectric material, such as silicon oxide, is deposited over the gate and surface of the substrate and etched back to form spacers on either side of the gate. Next, a thin oxide layer is deposited over the gate and surface of the substrate to protect the gate and underlying areas of the substrate from subsequent etch processes. A layer of polysilicon is deposited over the thin oxide layer to protect the CMOS region during subsequent bipolar transistor processing.
In the above approach, an opening in the layer of polysilicon is formed over the collector in the bipolar region of the substrate by patterning and etching the layer of polysilicon. A wet dip is then used to remove the thin oxide layer in the opening. A layer of base material, such as polycrystalline SiGe, is then epitaxially deposited over the layer of polysilicon and in the opening to form a SiGe base. An emitter is formed on the SiGe base in the opening, and unwanted base material is removed to form contacts for the SiGe base. After formation of the SiGe HBT, the protective layer of polysilicon is removed from the surface of the substrate.
In the above approach, a layer of dielectric material is deposited and etched back to form spacers for the PFET gate, and a separate layer of polysilicon is deposited to protect the CMOS region during formation of the bipolar transistor. Thus, in the above approach, the layer of dielectric material is only utilized to form spacers for the PFET gate, while the layer of polysilicon only protects the CMOS region during bipolar transistor formation and thus must be removed after the bipolar transistor is formed. Thus, the deposition and removal of the layer of polysilicon increases overall process complexity by increasing process steps. The deposition and removal of the layer of polysilicon also increases processing time, which results in an increase in manufacturing cost.
Thus, there is a need in the art for a method for forming spacers in a CMOS region of a substrate in a BiCMOS process that reduces process flow complexity and manufacturing cost.